Efficient Programming on Heterogeneous Accelerators

ABSTRACT

In this talk, I will first discuss how new mapping solutions, i.e., composing heterogeneous accelerators within system-on-chip with both FPGAs and AI tensor cores, achieve orders of magnitude energy efficiency gains when compared to monolithic accelerator mapping designs for deep learning applications. Then, I will apply such novel mapping solutions to show how design space explorations are performed when composing heterogeneous accelerators in latency-through tradeoff analysis. I will further discuss how such mapping and scheduling can be applied to other computing systems, such as GPUs

BIOGRAPHY

Peipei Zhou is currently an Assistant Professor at the School of Engineering, Brown University. She received her Ph.D. in Computer Science (2019) and M.S. in Electrical and Computer Engineering (2014) from UCLA, and her B.S. in Electrical and Computer Engineering (2012) from Southeast University. Her research investigates architecture, programming abstraction, and design automation tools for reconfigurable computing and heterogeneous computing. She has published 40 papers in IEEE/ACM computer system and design automation conferences and journals. Her work has won the 2019 IEEE TCAD Donald O. Pederson Best Paper Award. Other awards include the 2024 ACM/IEEE IGSC Best Viewpoint Paper, the 2025 ACM/SIGDA FPGA Best Paper Nominee, the 2018 IEEE ISPASS Best Paper Nominee, and the 2018 IEEE/ACM ICCAD Best Paper Nominee.