Abstract: As semiconductor feature sizes shrink into the nanometer scale regime, even conventional device behavior becomes increasingly complicated as new physical phenomena at short dimensions occur, and limitations in material properties are reached. In addition to the problems related to the understanding of actual operation of ultra-small devices, the reduced feature sizes require more complicated and time-consuming manufacturing processes. This fact signifies that a pure trial-and-error approach to device optimization will become impossible since it is both too time consuming and too expensive.  Since computers are considerably cheaper resources, simulation is becoming an indispensable tool for the device engineer.  Besides offering the possibility to test hypothetical devices which have not (or could not) yet been manufactured, simulation offers unique insight into device behavior by allowing the observation of phenomena that cannot be measured on real devices. Computational Electronics in this context refers to the physical simulation of semiconductor devices in terms of charge transport and the corresponding electrical behavior.

In this talk I will present highlights on the research activities within my group, including self-heating effects in 28nm technology FD SOI devices at cryogenic temperatures, modelling electrostatics and transport in SiGeSn material system, random dopant and unintentional dopant fluctuations modelling for nanoscale FinFET devices, and treatment of quantum confinement effects in particle-based device simulations using the effective potential approach.