ECE Spring Seminar Series
DSS Speaker, Vishal Saxena, University of Idaho
Title: Sustaining Advances in Integrated Circuits in the Post CMOS-Scaling Era
Data bandwidth requirements in information and communication technology industry keep increasing exponentially as we transition into the era of AI and ‘Big Data’ processing. This growth directly impacts the cost and the energy consumption of the computing and communication infrastructure. Moreover, this unabated demand in data processing and transfer faces challenges due to the imminent end of Moore’s law of CMOS scaling, coupled with saturation in innovation seen in mixed-signal and RF IC architectures. On the other hand, silicon photonics technology, which can be used to fabricate optical devices using CMOS-compatible technology, not only brings integrated photonic chips into mass production but can also save a significant amount of power to move massive amount of data in the form of photons over 1000× capacity than in the form of electrons. Silicon-based integrated photonics is seen as the enabler for low-cost photonic interconnect ICs into the racks in the future data centers, chip-to-chip transfer on the motherboard and backplanes, and even into future many-core processors. Furthermore, ultra-broadband signal processing enabled by integrated hybrid electronic-photonic circuits allows novel growth and innovation drivers in RF and mmWave transceivers, scalable to large beamforming arrays.
In this talk, Dr. Saxena will highlight his ongoing research in CMOS Photonic Mixed-Signal Integrated Circuits and RF/mmWave Photonic Integrated Circuits. He will present cross-physical layer high-speed circuits for sustaining growth in data rates while improving their energy-efficiency, both for wireline and well as wireless links. The presenter will also briefly introduce his research on ultra-low-power Neuromorphic System-on-a-Chip (NeuSoC) for embedded Artificial Intelligence at the Edge.
Keywords: CMOS photonics, RF/mmWave photonics, optical interconnects, ultra-low-power AI, in-memory computing.
Vishal Saxena is the Micron Endowed Professor of Microelectronics and Associate Professor of Electrical and Computer Engineering at the University of Idaho. He obtained his B. Tech. degree in Electrical Engineering from Indian Institute of Technology, Madras in 2002. Subsequently, he graduated with a Ph.D. from Boise State University, ID in 2010 in the area of wideband Delta-Sigma ADC design. In between, he has held design positions in analog IC startups. At the University of Idaho, he directs the Analog Mixed-Signal and Photonic Integrated Circuits (AMPIC) Lab, and the Neural Inspired and Brain-Inspired Technologies (NeuBiT) group. He teaches courses on Analog, Mixed-Signal, and RF IC design. Dr. Saxena received the 2015 NSF CAREER, 2016 AFOSR Young Investigator Program (YIP) award, and 2019 DARPA Young Faculty Award (YFA) for his work on CMOS photonic integrated circuits, and Idaho’s accomplished under 40 (AU40) award in 2016. He is a member of IEEE and an Associate Editor for IEEE TCAS-II journal. He currently serves on the steering committees of IEEE MWSCAS, ISCAS, and WMED conferences.
His research interests include Energy-efficient cross-physical layer links, CMOS photonic interconnects, RF/mmWave photonics, Continuous-time Delta-Sigma ADCs, and low-power VLSI for enabling embedded Artificial Intelligence.
Monday, April 8, 2019 at 11:15am to 12:05pm
Evans Hall, Evans 204
Evans Hall, University of Delaware, Newark, DE 19716, USA